1. Field of the Invention
The present invention relates generally to an electrically erasable non-volatile semiconductor memory, and more particularly to a memory cell structure useful for a flash EEPROM of a NOR type etc., in which a writing operation is executed by injecting hot electrons.
2. Description of the Background Art
A memory cell of an EEPROM (Electrically Erasable Programable Read Only Memory) normally involves the use of an FETMOS structure in which a floating gate and a control gate are stacked via an insulating film on a semiconductor substrate.
Among a variety of EEPROMs, normally a hot electron injection is utilized in a NOR type flash memory cell. That is, in writing mode, the memory cell is set in on-state in which a large channel current flows. In this state, Hot electrons are thereby generated in a pinch-off region in the vicinity of a drain, and are injected into the floating gate. An erasing operation is carried out, for example, by releasing the electrons accumulated in the floating gate towards a source by use of a Fowler-Nordheim tunnel current mechanism.
In the thus structured hot electron injection type memory cell, it is required that a diffusion distance, an impurity concentration and an overlap with the floating gate are optimally set with respect to the source and drain regions in order to optimize write and erasure characteristics. For example, in the case of the memory cell having a structure to perform an erasure by releasing the electrons accumulated in the floating gate towards the source, a large overlap with the floating gate is needed with respect to the source region. Furthermore, since a large channel current flows during the writing operation, it is required that a source resistance be sufficiently low. It is therefore desired that the source region be deeper and higher in concentration than the drain region. Moreover, when the electrons are trapped in a gate insulating film in the vicinity of the drain with a repetition of the writing operations, an offset might occur in the drain side, thereby inducing decreases in a write efficiency to the memory cell and in current drivability as well. In order to prevent these decreases from occurring, an overlap with the floating gate with respect to the drain region, which is not so much as the source region, is required.
On the other hand, there was proposed a structure for increasing the overlap with the floating gate in the drain region with respect to a hot electron injection type non-volatile memory cell (refer to, e.g., Japanese Patent Application Laid-Open Publication Nos.5-343701 (1993) and 6-252414 (1994)).
Furthermore, there exists a non-volatile memory which is not classified as the hot electron injection type, wherein the electrons are injected and released by the tunnel current between the drain region and the floating gate. In the case of this type of memory cell, it is effective that the overlap of the drain region with the floating gate takes an asymmetric structure set as large as the source region in the case of releasing the electrons towards the source (refer to, e.g., Japanese Patent Application Laid-Open Publication No.5-36990(1993)). Still further, there is, though not a method of utilizing the hot electrons generated by the channel current in an on-state bias, a proposal for increasing similarly the overlap of the drain region with the floating gate with respect to the memory cell utilizing the hot electrons generated by avalanche (refer to Japanese Patent Application Laid-Open Publication No.5-55599).
As explained above, in the conventional non-volatile memory cell utilizing the electron implantation from the drain region as typified by the hot electron injection, there are required the respective overlaps of the source and drain regions with the floating gate. Moreover, it is also proposed from a various points of view that a geometry between the floating gate and the source and drain regions takes the asymmetric structure. The progress of the technology of down scaling the semiconductor devices has been remarkable over the recent years, however, if making an attempt of attaining a high-integration EEPROM by use of the down scaling technology, there might arise a situation in which an effective channel length can not be ensured in the case of increasing the overlaps of the source and drain regions with the floating gate. Furthermore, when trying to keeping the effective channel length Leff to some extent, a gate length L elongates corresponding to a proportion of the overlaps of the source and drain regions with the floating gate, and it is therefore difficult to reduce a size of the memory cell.